10 Bits multiplier using gate level modeling (verilog)

 10 Bits Multiplier code

module mul10bit(A,B,P);

    input [9:0] A,B;
    output [20:0] P;
   reg [4:0] C,D,E,F;
   wire [9:0] P11,P12,P13,P14;
      wire [31:0] CA;
      wire [17:0] M;
      always @(A)
  assign C=A[4:0];
always @(A)
assign  D=A[9:5];
  always @(B)
  assign E=B[4:0];
always @(B)
assign  F=B[9:5];

bit5mul FIRST1(C,E,P11);
bit5mul SECOND2(D,E,P12);
bit5mul FORTH3(C,F,P13);
bit5mul FIFTH4(D,F,P14);

assign P[0]=P11[0];
assign P[1]=P11[1];
assign P[2]=P11[2];
assign P[3]=P11[3];
assign P[4]=P11[4];
fulladder SS1(P11[5],P12[0],P13[0],CA[0],P[5]);

fulladder SS22(P11[6],P12[1],P13[1],CA[1],M[0]);
fulladder SS11(1'b0,M[0],CA[0],CA[2],P[6]);

fulladder SS23(P11[7],P12[2],P13[2],CA[3],M[1]);
fulladder SS241(CA[1],M[1],CA[2],CA[4],P[7]);

fulladder SS25(P11[8],P12[3],P13[3],CA[5],M[2]);
fulladder SS26(CA[4],M[2],CA[3],CA[6],P[8]);

fulladder SS27(P11[9],P12[4],P13[4],CA[7],M[3]);
fulladder SS28(CA[6],M[3],CA[5],CA[8],P[9]);

fulladder SS29(P14[0],P12[5],P13[5],CA[9],M[4]);
fulladder SS288(CA[7],M[4],CA[8],CA[10],P[10]);

fulladder SS2777(P14[1],P12[6],P13[6],CA[11],M[5]);
fulladder SS248(CA[9],M[5],CA[10],CA[12],P[11]);


fulladder SS299(P14[2],P12[7],P13[7],CA[13],M[6]);
fulladder SS2488(CA[12],M[6],CA[11],CA[14],P[12]);


fulladder SS278(P14[3],P12[8],P13[8],CA[15],M[7]);
fulladder SS2465(CA[13],M[7],CA[14],CA[16],P[13]);

fulladder SS2786(P14[4],P12[9],P13[9],CA[17],M[8]);
fulladder SS24564(CA[15],M[8],CA[16],CA[18],P[14]);

fulladder SS24546(CA[17],CA[18],P14[5],CA[19],P[15]);


fulladder SS2768(P14[6],CA[19],1'b0,CA[20],P[16]);

fulladder SS267(P14[7],CA[20],1'b0,CA[21],P[17]);
fulladder SS2674(P14[8],CA[21],1'b0,CA[22],P[18]);
fulladder SS2676(P14[9],CA[22],1'b0,P[20],P[19]);
endmodule

module fulladder(a,b,c,carry,out);
    input a,b,c;
    output carry,out;
    wire w1,w2,w3;
    and g1(w2,a,b);
    xor g2(w1,a,b);
    and g3(w3,w1,c);
    xor g4(out, w1,c);
    or g5(carry,w3,w2);
endmodule

 module bit5mul(A1,B1,P1);
 input [4:0] A1,B1;
 output [9:0] P1;
 wire [24:0] W;
 wire [12:0]S;
 wire [18:0] C;
 //andgate instantiations 
 and g1(W[0],A1[0],B1[0]);
 and g2(W[1],A1[1],B1[0]);
  and g3(W[2],A1[2],B1[0]);
   and g4(W[3],A1[3],B1[0]);
    and g5(W[4],A1[4],B1[0]);
     and g6(W[5],A1[0],B1[1]); 
      and g7(W[6],A1[1],B1[1]);
       and g8(W[7],A1[2],B1[1]);
        and g9(W[8],A1[3],B1[1]);
         and g10(W[9],A1[4],B1[1]);
          and g11(W[10],A1[0],B1[2]);
           and g12(W[11],A1[1],B1[2]);
            and g13(W[12],A1[2],B1[2]);
             and g14(W[13],A1[3],B1[2]);
              and g15(W[14],A1[4],B1[2]);
               and g16(W[15],A1[0],B1[3]);
                and g17(W[16],A1[1],B1[3]);
                 and g18(W[17],A1[2],B1[3]);
                  and g19(W[18],A1[3],B1[3]);
                   and g20(W[19],A1[4],B1[3]);
                    and g21(W[20],A1[0],B1[4]);
                     and g22(W[21],A1[1],B1[4]);
                      and g23(W[22],A1[2],B1[4]);
                       and g24(W[23],A1[3],B1[4]);
                        and g25(W[24],A1[4],B1[4]);
       assign P1[0]=W[0];
//full adders instatiations
fulladder F0(1'b0,W[1],W[5],C[0],P1[1]);

fulladder F11(C[0],W[2],W[6],C[1],S[0]);
fulladder F12(1'b0,S[0],W[10],C[2],P1[2]);

fulladder F21(C[2],W[3],W[7],C[3],S[1]);
fulladder F22(C[1],S[1],W[11],C[4],S[2]);
fulladder F23(1'b0,S[2],W[15],C[5],P1[3]);

fulladder F31(C[3],W[4],W[8],C[6],S[3]);
fulladder F32(C[4],S[3],W[12],C[7],S[4]);
fulladder F33(C[5],S[4],W[16],C[8],S[5]);
fulladder F34(1'b0,S[5],W[20],C[9],P1[4]);

fulladder F41(C[6],W[9],W[13],C[10],S[6]);
fulladder F42(C[7],S[6],W[17],C[11],S[7]);
fulladder F43(C[8],S[7],W[21],C[12],S[8]);
fulladder F435(C[9],S[8],1'b0,C[13],P1[5]);

fulladder F51(C[10],W[14],W[18],C[14],S[9]);
fulladder F524(C[11],S[9],W[22],C[15],S[10]);
fulladder F52(C[12],C[13],S[10],C[16],P1[6]);

fulladder F61(C[14],W[19],W[23],C[17],S[11]);
fulladder F617(C[15],S[11],C[16],C[18],P1[7]);

fulladder F1(C[17],C[18],W[24],P1[9],P1[8]);
endmodule

module testbencd_mul10();

    reg  [9:0] A,B;
    wire [20:0] P;
    mul10bit fgf(A,B,P);
    initial
    begin
        A=10'b 0000000000;  B=10'b 0000000000;
        #10 A=10'b 1011001101;  B=10'b 1111111111;
        #10 A=10'b 1111111111;  B=10'b 1111111111;
        #10 A=10'b 1011001101;  B=10'b 1111111110;
    end
endmodule

Code of serial in serial out shift register in verilog

Code of serial in serial out shift register in verilog

module dff(clk,reset,di,doo); // D Flip Flop Code
 input clk,reset,di;
    output doo;
    reg doo;
    always @(posedge clk)
    if (reset==0)
    doo<=0;
    else
    doo<=di;
endmodule

module siso(d,clk,reset,out);//code of the register
    input d;
    input clk,reset;
    output  out;
    reg  out;
    wire [2:0] q;
    dff call1(clk,reset,d,q[0]);
    dff call2(clk,reset,q[0],q[1]);
    dff call3(clk,reset,q[1],q[2]);
    dff call4(clk,reset,q[2],out);
    endmodule

module testbench();
reg d;
    reg clk,reset;
    wire out;
    siso call(d,clk,reset,out);
    always #2 clk=~clk;
    initial
    begin
        reset=0;clk=0;
        #10 reset=1;
        #10 d=1;
        #10 d=0;
        #10 d=0;
        #10 d=1;
   end
endmodule

module mux2_1(y,z,e,I0,clk,reset);
    input clk,reset;
input I0;
input [7:0]e;
wire I1;
    output y;
    output [7:0]z;
     reg y;
    assign z=e<<6;
     xor gh(I1,y,I0);
    always@(posedge clk)
    begin
        if (reset==0)
        y=0;
        else
        y=I1;
    end
 
endmodule

module masab();
    reg clk,reset;
    reg I0;
    wire y;
     wire [7:0]z;
  reg [7:0]e;
 mux2_1 fkgf(y,z,e,I0,clk,reset);
always #2 clk=~clk;
    initial
    begin
        e=7'b1101010;
        reset=0;clk=0;
         #10 reset=1; I0=0;
       
         #20 I0=1;
    end
endmodule

Proteaus Stimulation of Traffic Light

555 Timer its pin configurations and Mode of operations (astable mode)

555 Timer

            The 555 Timer is a popular and useful timing device use to generate signal pulse or long time delays or used to generate precise time duration of high and low output from microseconds to hour. The 555 Timer which gets its name from the three 5kΩ resistors it uses to generate the two comparators reference voltage. Now the below table explain its pin configuration.

Internal structure of 555 Timer

            It is basically composed of two comparator and SR flip flop. Comparator is device which simply compares two input voltages .The comparator or analog device with digital output. Secondly the flip flop is the digital building block that remember the last thing happen to it. The SR flip flop respond in two ways If the set input goes high the output of 555 Timer is stay high. And if the reset input goes high the output of 555 Timer is stay low.

Pin No.	Name	Function
Pin 1	Ground	This pin should be connected to ground.
Pin 2	Trigger	This pin is the input to the lower comparator and is used to set the latch and this pin is dragged from the negative input of the comparator. The Lower comparator output is connected to SET pin of flip-flop. A negative pulse (< Vcc/3) on this Pin sets the Flip flop and output goes High.
Pin 3	Output	The pin where load is connected and it has no special function.
Pin 4	Reset	There is a flip-flop in the timer chip. Reset pin is directly connected to MR (Master Reset) of the flip-flop. This is a active Low pin and normally connected to Vcc for preventing accidental Reset.
Pin 5	Control Voltage	The control pin is connected from the negative input pin of comparator one. Output Pulse width can be controlled by applying voltage at this Pin, irrespective of RC network. Normally this pin is pulled down with a capacitor (0.01uF), to avoid unwanted noise interference with the working
Pin 6	Threshold	Threshold pin voltage determines when to reset the flip-flop in the timer. The threshold pin is drawn from positive input of upper comparator. If the control pin is open, then a voltage equal to or greater than VCC*(2/3) will reset the flip-flop. So the output goes low.
Pin 7	Discharge	This pin is drawn from the open collector of transistor. Since the transistor (on which discharge pin got taken, Q1) got its base connected to Qbar. Whenever the output goes low or the flip-flop gets reset, the discharge pin is pulled to ground and capacitor discharges.
Pin 8	Power Supply (Vcc)	It is connected to positive voltage (+3.6v to +15v).

Mode of Operations

Astable mode

                       An astable circuit has no stable state - hence the name "astable". The output continually switches state between high and low without any intervention from the user, called a 'square' wave. 

Circuit Diagram

Monostable mode

                        A monostable circuit produces one pulse of a set length in response to a trigger input such as a push button. The output of the circuit stays in the low state until there is a trigger input, hence the name "monostable" meaning "one stable state".

Bistable Mode (or Schmitt Trigger)
     

                   A bistable mode or what is sometimes called a Schmitt Trigger, has two stable states, high and low. Taking the Trigger input low makes the output of the circuit go into the high state. Taking the Reset input low makes the output of the circuit go into the low state.

Working of Astable Mode

                          Now when the trigger pin voltage is below 3 volt the output of the flip flip goes high, the signal is provided to the set terminal of flip flop. The output remain high until a signal is provided to reset of flip flop and discharge switch remain off. When the threshold pin voltage goes above  6 volt  (it is because of the charging of the capacitor)  the reset pin get a signal and set terminal of flip flop set to zero and output set to low. Gradually the capacitor discharge and when the voltage comes below 3 volt set terminal get the signal when output get high and the cycle continue to give a rectangular wave form.

Overall in astable mode the circuit work as an oscillating circuit. The output form a rectangular wave form with a particular frequency, the factor which determine frequency are the capacitor and the two resistor which attach in series. The changing of the valve of these parameter changes frequency.

Uses of 555 Timer

·         IR base security Alarm.

·         Automatic Rain Sensing Wiper Circuit using 555 Timer IC.

·         Clap On Clap Off Switch.

Pulse generation, and Oscillator applications.

D Flip Flop IC and its Pin Configuration (74HC74 IC, 74SL74)

D Flip Flop Using 74HC74 IC

The 74HC74 is a dual D flip flop IC. Therefore at a time we can handle two bit of data with it. It have two terminal which are asynchronous and change the value of output without being effected by clock signal. These are set and reset terminals. Now Its Pin configuration

Pin	Symbol	Description
1	1 SD	Asynchronous reset direct input (active low).
2	1D	Data input.
3	1CP	Clock input
4	1SD	Asynchronous set direct input (active low).
5	1Q	Output
6	1Q	Complement Output
7	GND	Ground
8	2Q	Complement Output
9	2Q	Output
10	2SD	Asynchronous set direct input  (active low)
11	2CP	Clock input
12	2D	Data input
13	2RD	Asynchronous reset direct input  (active low)
14	VCC	Supply voltage

 Application and Uses of D FLIP Flop

·         D Flip Flop is use as Frequency Divider.

In registers the d flip flop is use to store and transfer data. Each flip flop store single bit of data.