10 Bits Multiplier code
module mul10bit(A,B,P);
input [9:0] A,B;output [20:0] P;
reg [4:0] C,D,E,F;
wire [9:0] P11,P12,P13,P14;
wire [31:0] CA;
wire [17:0] M;
always @(A)
assign C=A[4:0];
always @(A)
assign D=A[9:5];
always @(B)
assign E=B[4:0];
always @(B)
assign F=B[9:5];
bit5mul FIRST1(C,E,P11);
bit5mul SECOND2(D,E,P12);
bit5mul FORTH3(C,F,P13);
bit5mul FIFTH4(D,F,P14);
assign P[0]=P11[0];assign P[1]=P11[1];
assign P[2]=P11[2];
assign P[3]=P11[3];
assign P[4]=P11[4];
fulladder SS1(P11[5],P12[0],P13[0],CA[0],P[5]);
fulladder SS22(P11[6],P12[1],P13[1],CA[1],M[0]);
fulladder SS11(1'b0,M[0],CA[0],CA[2],P[6]);
fulladder SS23(P11[7],P12[2],P13[2],CA[3],M[1]);
fulladder SS241(CA[1],M[1],CA[2],CA[4],P[7]);
fulladder SS25(P11[8],P12[3],P13[3],CA[5],M[2]);
fulladder SS26(CA[4],M[2],CA[3],CA[6],P[8]);
fulladder SS27(P11[9],P12[4],P13[4],CA[7],M[3]);
fulladder SS28(CA[6],M[3],CA[5],CA[8],P[9]);
fulladder SS29(P14[0],P12[5],P13[5],CA[9],M[4]);
fulladder SS288(CA[7],M[4],CA[8],CA[10],P[10]);
fulladder SS2777(P14[1],P12[6],P13[6],CA[11],M[5]);
fulladder SS248(CA[9],M[5],CA[10],CA[12],P[11]);
fulladder SS299(P14[2],P12[7],P13[7],CA[13],M[6]);
fulladder SS2488(CA[12],M[6],CA[11],CA[14],P[12]);
fulladder SS278(P14[3],P12[8],P13[8],CA[15],M[7]);
fulladder SS2465(CA[13],M[7],CA[14],CA[16],P[13]);
fulladder SS2786(P14[4],P12[9],P13[9],CA[17],M[8]);
fulladder SS24564(CA[15],M[8],CA[16],CA[18],P[14]);
fulladder SS24546(CA[17],CA[18],P14[5],CA[19],P[15]);
fulladder SS2768(P14[6],CA[19],1'b0,CA[20],P[16]);
fulladder SS267(P14[7],CA[20],1'b0,CA[21],P[17]);
fulladder SS2674(P14[8],CA[21],1'b0,CA[22],P[18]);
fulladder SS2676(P14[9],CA[22],1'b0,P[20],P[19]);
endmodule
module fulladder(a,b,c,carry,out);
input a,b,c;
output carry,out;
wire w1,w2,w3;
and g1(w2,a,b);
xor g2(w1,a,b);
and g3(w3,w1,c);
xor g4(out, w1,c);
or g5(carry,w3,w2);
endmodule
module bit5mul(A1,B1,P1);
input [4:0] A1,B1;
output [9:0] P1;
wire [24:0] W;
wire [12:0]S;
wire [18:0] C;
//andgate instantiations
and g1(W[0],A1[0],B1[0]);
and g2(W[1],A1[1],B1[0]);
and g3(W[2],A1[2],B1[0]);
and g4(W[3],A1[3],B1[0]);
and g5(W[4],A1[4],B1[0]);
and g6(W[5],A1[0],B1[1]);
and g7(W[6],A1[1],B1[1]);
and g8(W[7],A1[2],B1[1]);
and g9(W[8],A1[3],B1[1]);
and g10(W[9],A1[4],B1[1]);
and g11(W[10],A1[0],B1[2]);
and g12(W[11],A1[1],B1[2]);
and g13(W[12],A1[2],B1[2]);
and g14(W[13],A1[3],B1[2]);
and g15(W[14],A1[4],B1[2]);
and g16(W[15],A1[0],B1[3]);
and g17(W[16],A1[1],B1[3]);
and g18(W[17],A1[2],B1[3]);
and g19(W[18],A1[3],B1[3]);
and g20(W[19],A1[4],B1[3]);
and g21(W[20],A1[0],B1[4]);
and g22(W[21],A1[1],B1[4]);
and g23(W[22],A1[2],B1[4]);
and g24(W[23],A1[3],B1[4]);
and g25(W[24],A1[4],B1[4]);
assign P1[0]=W[0];
//full adders instatiations
fulladder F0(1'b0,W[1],W[5],C[0],P1[1]);
fulladder F11(C[0],W[2],W[6],C[1],S[0]);
fulladder F12(1'b0,S[0],W[10],C[2],P1[2]);
fulladder F21(C[2],W[3],W[7],C[3],S[1]);
fulladder F22(C[1],S[1],W[11],C[4],S[2]);
fulladder F23(1'b0,S[2],W[15],C[5],P1[3]);
fulladder F31(C[3],W[4],W[8],C[6],S[3]);
fulladder F32(C[4],S[3],W[12],C[7],S[4]);
fulladder F33(C[5],S[4],W[16],C[8],S[5]);
fulladder F34(1'b0,S[5],W[20],C[9],P1[4]);
fulladder F41(C[6],W[9],W[13],C[10],S[6]);
fulladder F42(C[7],S[6],W[17],C[11],S[7]);
fulladder F43(C[8],S[7],W[21],C[12],S[8]);
fulladder F435(C[9],S[8],1'b0,C[13],P1[5]);
fulladder F51(C[10],W[14],W[18],C[14],S[9]);
fulladder F524(C[11],S[9],W[22],C[15],S[10]);
fulladder F52(C[12],C[13],S[10],C[16],P1[6]);
fulladder F61(C[14],W[19],W[23],C[17],S[11]);
fulladder F617(C[15],S[11],C[16],C[18],P1[7]);
fulladder F1(C[17],C[18],W[24],P1[9],P1[8]);
endmodule
module testbencd_mul10();
reg [9:0] A,B;wire [20:0] P;
mul10bit fgf(A,B,P);
initial
begin
A=10'b 0000000000; B=10'b 0000000000;
#10 A=10'b 1011001101; B=10'b 1111111111;
#10 A=10'b 1111111111; B=10'b 1111111111;
#10 A=10'b 1011001101; B=10'b 1111111110;
end
endmodule
No comments:
Post a Comment