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Sunday, November 13, 2016

Code of serial in serial out shift register in verilog

Code of serial in serial out shift register in verilog


module dff(clk,reset,di,doo); // D Flip Flop Code
 input clk,reset,di;
    output doo;
    reg doo;
    always @(posedge clk)
    if (reset==0)
    doo<=0;
    else
    doo<=di;
endmodule

module siso(d,clk,reset,out);//code of the register
    input d;
    input clk,reset;
    output  out;
    reg  out;
    wire [2:0] q;
    dff call1(clk,reset,d,q[0]);
    dff call2(clk,reset,q[0],q[1]);
    dff call3(clk,reset,q[1],q[2]);
    dff call4(clk,reset,q[2],out);
    endmodule

module testbench();
reg d;
    reg clk,reset;
    wire out;
    siso call(d,clk,reset,out);
    always #2 clk=~clk;
    initial
    begin
        reset=0;clk=0;
        #10 reset=1;
        #10 d=1;
        #10 d=0;
        #10 d=0;
        #10 d=1;
   end
endmodule

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